Multiprocessor systems configured as system LSIs each have multiple processor units (hereinafter referred to as central processing units (CPUs)) implemented on a chip. The multiple CPUs perform, for example, parallel processing and cooperative processing. The CPUs pass the processing to each other in response to interrupt functioning as a trigger. In a typical multiprocessor system configured as a system LSI in the related art, an interrupt-request destination CPU submits an interrupt request to an interrupt-request destination CPU that is specified by the interrupt-request destination CPU. The interrupt-request destination CPU stops the processing that is being performed in response to the interrupt request and performs certain interrupt processing, for example, taking over of the processing that has been performed by the interrupt-request destination CPU.
The multiprocessor system is required to operate in a low power consumption state to achieve power saving control. The low power consumption state in which the power consumption by each CPU is reduced means adopting at least one of the following three methods: (1) a clock signal to be applied to each CPU is stopped or the frequency of the clock signal is decreased, (2) a clock signal is applied to each CPU but a clock signal to be applied to each circuit excluding some circuits including an interrupt determining circuit in the CPU is stopped, and (3) the power voltage to each CPU is decreased or is set to zero volts.
The above low power consumption state is generally called, for example, a sleep state, a shutdown state, a standby state, or a power-down state. Specifically, the operations of CPUs that are not required to perform real-time processing, among the CPUs in the multiprocessor system configured as a system LSI, are restricted to reduce the power consumption.
Japanese Laid-open Patent Publication No. 2004-78642 discloses a circuit capable of changing the length of an interrupt signal into a length that may be recognized by each processor in response to a variation in frequency of the internal operation of the processor, caused by a reduced power consumption.
Japanese Laid-open Patent Publication No. 3-81834 discloses an interrupt control apparatus in a multiprocessor system, which simultaneously transmits interrupt signals to multiple processors.
Japanese Laid-open Patent Publication No. 2005-332402 discloses a technology in a multiprocessor system, in which a main processor arranging the processing schedule monitors each sub-processor and reallocates processing to the sub-processors depending on the situation so that the operation of the entire multiprocessor system may be ensured even if an error occurs in the sub-processor.